1. Field of the Invention
The present invention relates to the field of mixed signal integrated circuits and, more particularly, to noise management in an analog-to-digital converter.
2. Background of the Related Art
The use of analog-to-digital converters (A/D converters or ADCs) to convert analog signals into digital signals is well known in the art. State-of-the-art practice is to fabricate an ADC on a single integrated circuit chip. Generally, an ADC samples an analog signal at a sampling rate which is twice the highest frequency component being sampled. This is known as the Nyquist rate. The sampled signal is processed and converted into a digital format for output from the converter.
Another type of ADC employs an oversampling technique in which the analog input signal is sampled at a much higher rate than the Nyquist rate. The higher sampling rate improves the performance of the ADC for signal conversion and processing. One commonly used oversampling type of ADC uses a delta-sigma (.DELTA..SIGMA.) modulator for oversampling the analog input. The oversampled output of the .DELTA..SIGMA. modulator is coupled to a decimator, which employs a low-pass filtering technique to extract the lower frequency components to generate a converted digital output signal at the Nyquist rate.
It is appreciated that ADCs are mixed-signal devices in that both analog and digital signals are present in the ADC. In a mixed-signal design, where both the analog and digital circuitry reside on a monolithic integrated circuit, one main area of design concern is noise management. In mixed-signal devices, it is desirable to minimize digital circuit activity during the time the analog circuitry is sampling the analog input signal. Otherwise, noise generated by the switching of the digital circuitry will couple into the analog circuitry, for example through the substrate. In order to prevent the digital noise at the analog sampling times or events, techniques have been designed to circumvent the noise coupling.
In one technique, the digital clock is delayed with respect to the analog clock so that the digital circuitry is triggered by the digital clock, only after the analog sampling has occurred. This technique allows analog sampling to occur just prior to the commencement of the operation of the digital circuitry and in which the digital circuitry is permitted to complete its operation prior to the next analog sampling event. Another technique simply drops (removes) the digital clocking during the analog sampling event.
The above techniques are capable of achieving the desired result of managing noise presence during the analog sampling event, as long as the digital clocking frequency is noticeably higher than the analog clocking frequency. In earlier mixed-signal devices, this was typically the case. However, current generation ADCs employ analog clocking frequencies which are at or proximal to the digital clocking frequency. Hence, delaying or dropping the digital clock cycle is not an efficient solution.
One solution to address this problem is to implement a much faster digital circuitry. The present invention provides for a solution to manage noise generation during the analog sampling, without the need to implement a much faster digital circuitry.